1.1. Related Art
1.1.1. Multidimensional Arrays of Arithmetic and Logic Units
German Patent 196 51 075.9-53 describes processors, having a plurality of 2-dimensional or multidimensional arithmetic and logic units/cells. The computing power of such processors increases with the number of arithmetic arid logic units present. Therefore, an attempt is made to integrate as many arithmetic and logic units as possible on one chip, which increases the area required. With an increase in area, there is also a higher probability of a chip having a manufacturing defect making it useless. All arithmetic and logic units arranged in matrix form have this problem, e.g., including other known types such as DPGAs, Kress arrays, systolic processors and RAW machines; likewise, some digital signal processors (DSPs) having more than one arithmetic and logic unit.
At the same time, all the aforementioned types require a great deal of testing, i.e., to detect faults, an especially large number of test cases must be generated and tested with respect to the functioning of the cells and the networking. Traditional known methods such as BIST, boundary scan, etc. are difficult to integrate because of the large number of test vectors and they are also too time consuming and take up too much space.
1.1.2. Standard Processors
Standard processors such as the known x86 series, MIPS or ALPHA have a plurality of arithmetic and logic units which are driven at the same time by a VLIW command or with a time offset. In the future, the number of integrated units (integer units) and floating point units will continue to increase. Each unit must be tested adequately and must be largely free of defects.
1.2. Problems
1.2.1. Multidimensional Arrays of Arithmetic and Logic Units
Due to the increasing probability of defects with ‘large chips, either only a very small number of cells can be integrated or production costs will increase greatly due to the resulting rejects. Very large chips will reach a maximum area-beyond which a functional chip can no longer be produced. Due to the time consumed in testing according to traditional methods, there is a great increase in testing costs. Integrated BIST functions (built-in self-test) take up a great deal of area due to the high extra complexity, driving costs even higher and reducing manufacturing feasibility. In addition, this greatly increases the probability of a defect lying not within the actual function units but instead within the test structures.
1.2.2. Standard Processors
Due to the increasing number of arithmetic and logic units, there is also an increase in the probability of defects. This means more rejects, causing manufacturing costs to increase. With an increase in area and a related increase in the number of transistors used, there is also an increase in probability of failure during use.
With regard to testing complexity and implementation of BIST, the discussion above regarding “multidimensional arrays of arithmetic and logic units” also applies here.
1.3. Improvement Through the Present Invention; Object
According to the present invention, it is possible to replace defective cells by functional cells by functional cells and thus reduce rejects. A cell can be replaced either by the test systems at the time of manufacture of the chips or even by the user in the completely assembled system. Test vectors can be generated according to the BIST principle within the chip, or outside the unit according to a new method to save on space and costs. In addition, a possibility of chips automatically repairing defects without requiring any additional external tool is described. All the tests and repair can be performed during operation of the chips.